1. Field of the Invention
The present invention relates to a charge pump circuit with a plurality of booster stages, more specifically relates to a charge pump circuit applied to semiconductor circuits such as semiconductor memory device.
2. Description of the Related Art
A semiconductor memory device typically has a charge pump circuit for boosting the power supply voltage to a predetermined high voltage level supplied to several circuits in the memory device. FIG. 6 shows such a typical conventional charge pump circuit. As shown in FIG. 6, the charge pump circuit comprises a plurality of booster stages CP.sub.i (where i=1 to n). Each booster stage CP.sub.i comprises an NMOS transistor NT.sub.i and a pumping capacitor C.sub.i. The gate and drain of NMOS transistor NT.sub.i are connected together with one end of pumping capacitor C.sub.i. The other end of the pumping capacitor C.sub.i is connected to clock clk in odd-numbered stages, or to clock /clk in even-numbered stages. Clock clk alternately outputs power supply voltage V.sub.dd or 0 Volt at a predetermined period. Clock clk and clock /clk output mutually complementary values.
In a charge pump circuit thus comprised, the NMOS transistors NT.sub.i (i=1 to n) in the odd-numbered and those in the even-numbered stages alternately turn on and off with the periodic change in the clocks clk and /clk, and thus sequentially send a charge charged in the pumping capacitor C.sub.i to the next booster stage. Node ND.sub.i of each booster stage is thus sequentially boosted, and a predetermined high voltage boosted from the power supply voltage level V.sub.dd is ultimately obtained as the final output voltage V.sub.out.
FIG. 7 shows a potential of node ND.sub.i (where i=n-2 to n) of booster stages n-2 to n in the charge pump circuit shown in FIG. 6. Note that period A in FIG. 7 is the period in which clock clk outputs power supply voltage V.sub.dd and clock /clk outputs 0 V, and period B is the period in which clock clk outputs 0 V and clock /clk outputs power supply voltage V.sub.dd.
As shown in FIG. 7, in period B, the potential of node ND.sub.n-1 in stage n-1 is lower than the potential of node ND.sub.n-2 in stage n-2 by threshold voltage V.sub.th of NMOS transistor NT.sub.n. Likewise in period A, the potential of node ND.sub.n of stage n is lower than the potential of node ND.sub.n-1 in stage n-1 by threshold voltage V.sub.th.
Thus, there is a loss of threshold voltage V.sub.th in the boosting process from one booster stage to the next booster stage in a charge pump circuit shown in FIG. 6.
In a charge pump circuit of this type, the substrate bias effect influences operation of the charge pump circuit. That is, when the source voltage of the NMOS transistor rises, threshold voltage V.sub.th of the NMOS transistor rises due to the substrate bias effect. The threshold voltage V.sub.th of NMOS transistor NT.sub.n thus rises with an increase in the number of booster stages. Cumulative threshold voltage V.sub.th loss thus increases, and there is dramatic deterioration in booster efficiency. Switching operations may also not occur normally when threshold voltage V.sub.th rises. The number of booster stages is thus limited as a result of these problems, and a high output voltage cannot be achieved.
Japanese Patent Laid-Open Publication No. 08-322241 teaches a charge pump circuit for solving the aforementioned problems. FIG. 8 is a circuit diagram of the major parts of that charge pump circuit.
As shown in FIG. 8, each booster stage CP.sub.i (where i=1 to n) has a pumping capacitor C.sub.i, and a transfer gate PTG.sub.i for transferring charge charged in pumping capacitor C.sub.i. This transfer gate PTG.sub.i comprises a PMOS transistor. Each booster stage CP.sub.i also has a series circuit comprising a PMOS transistor PT.sub.i and an NMOS transistor NT.sub.i for controlling ON/OFF operation of transfer gate PTG.sub.i.
In the charge pump circuit comprised as shown in FIG. 8, clock clk is applied to the pumping capacitors C.sub.i in odd-numbered booster stages, and clock /clk is applied to pumping capacitors C.sub.i in even-number booster stages. With the change in clocks clk and /clk, the charge accumulated in pumping capacitor C.sub.i of each stage is passed through transfer gate PTG.sub.i and supplied to the next stage, thereby sequentially boosting node ND.sub.i in each stage.
During the boosting operation of this charge pump circuit, the ON/OFF operation of each transfer gate PTG.sub.i is controlled by means of the serial circuit including a PMOS transistor PT.sub.i and an NMOS transistor NT.sub.i. Thus, the problem of loss by threshold voltage V.sub.th during the boosting process as described above is solved.
N wells of the PMOS transistors constituting transfer gates PTG.sub.i are also formed separately for each PMOS transistor in the charge pump circuit shown in FIG. 8. Influence of the substrate bias effect on the PMOS transistors can thus be prevented.
It is not possible, however, to prevent influence of the substrate bias effect on NMOS transistors in this conventional charge pump circuit. Normal operation of the NMOS transistor in each following booster stage may thus be prevented by the substrate bias effect.
FIG. 9 shows the potential of nodes ND.sub.i (where i=n-2 to n) in booster stages n-2 to n in the charge pump circuit shown in FIG. 8. As shown in FIG. 9, the node potential of any booster stage in period A is different from the one in period B. For example, the potential in period A is higher than the potential in period B at node ND.sub.n-1. As a result, the potential of the N well to which the back gate of the PMOS transistor is connected changes according to the potential of clock clk, and current consumption in the N well occurs with this potential change. Because the area of the N well is large on the substrate, this current consumption becomes also large, and the efficiency of the charge pump circuit is thus degraded.
In the charge pump circuit described above, there are following problems: a voltage loss equivalent to the threshold voltage V.sub.th of the MOS transistors constituting the charge pump circuit; the substrate bias effect; and current consumption in the N wells as a result of a change in node potential as the clock output changes. Therefore, the efficiency drops and booster capacity is limited as a result of problems described above.